Affiliation:
1. Indian Institute of Technology Guwahati, Assam, India,
Abstract
Safety-critical real-time systems must meet stringent timing and fault-tolerance requirements. This article proposes a methodology for synthesizing an optimal preemptive multiprocessor aperiodic task scheduler using a formal supervisory control framework. The scheduler can tolerate single/multiple permanent processor faults. Further, the synthesis framework has been empowered with a novel BDD-based symbolic computation mechanism to control the exponential state-space complexity of the optimal exhaustive enumeration-oriented synthesis methodology.
Funder
TATA Consultancy Services (TCS) Research Fellowship Program
Publisher
Association for Computing Machinery (ACM)
Subject
Hardware and Architecture,Software
Cited by
12 articles.
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