Automated Bug Detection for High-level Synthesis of Multi-threaded Irregular Applications
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Published:2020-12
Issue:4
Volume:7
Page:1-26
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ISSN:2329-4949
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Container-title:ACM Transactions on Parallel Computing
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language:en
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Short-container-title:ACM Trans. Parallel Comput.
Author:
Fezzardi Pietro1,
Ferrandi Fabrizio1
Affiliation:
1. Dipartimento di Informazione, Elettronica e Bioingegneria – Politecnico di Milano, Milano, Italy
Abstract
Field Programmable Gate Arrays (FPGAs) are becoming an appealing technology in datacenters and High Performance Computing. High-Level Synthesis (HLS) of multi-threaded parallel programs is increasingly used to extract parallelism. Despite great leaps forward in HLS and related debugging methodologies, there is a lack of contributions in automated bug identification for HLS of multi-threaded programs. This work defines a methodology to automatically detect and isolate bugs in parallel circuits generated with HLS. The technique relies on hardware/software Discrepancy Analysis and exploits a pattern-matching algorithm based on Finite State Automata to compare multiple hardware and software threads. Overhead, advantages, and limitations are evaluated on designs generated with an open-source HLS compiler supporting OpenMP.
Publisher
Association for Computing Machinery (ACM)
Subject
Computational Theory and Mathematics,Computer Science Applications,Hardware and Architecture,Modeling and Simulation,Software
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