Author:
Bai Xiaoliang,Visweswariah Chandu,Strenski Philip N.
Cited by
6 articles.
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1. Power efficient network selector placement in control plane of multiple networks-on-chip;The Journal of Supercomputing;2021-10-25
2. Area-energy tradeoffs of logic wear-leveling for BTI-induced aging;Proceedings of the ACM International Conference on Computing Frontiers;2016-05-16
3. Effect of Variations and Variation Tolerance in Logic Circuits;Low-Power Variation-Tolerant Design in Nanometer Silicon;2010-10-25
4. Variation-aware multimetric optimization during gate sizing;ACM Transactions on Design Automation of Electronic Systems;2009-08
5. Winning the Power Struggle in an Uncertain Era;Closing the Power Gap Between ASIC & Custom;2007