A framework for systematic validation and debugging of pipeline simulators
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Published:2005-07
Issue:3
Volume:10
Page:462-491
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ISSN:1084-4309
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Container-title:ACM Transactions on Design Automation of Electronic Systems
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language:en
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Short-container-title:ACM Trans. Des. Autom. Electron. Syst.
Author:
Roy Arnab1,
Panda S. K.1,
Kumar Rajeev1,
Chakrabarti P. P.1
Affiliation:
1. Indian Institute of Technology Kharagpur, Kharagpur, WB
Abstract
Microprocessor pipeline simulation at the system level is an extremely important activity in the architecture exploration process. In this article, we address the problem of validating and debugging a pipeline simulator from the specific perspective of instruction scheduling. We propose a general framework for a systematic validation process and show that the assumptions made are justified for most standard pipeline models. The framework does not need any formal specification of the pipeline logic and hence can be readily integrated into the simulation and iteration-based architectural design space exploration process. We propose a concept of semantic equivalence between two simulations called
D* equivalence
which effectively captures the dataflow between instructions through registers. We then proceed to propose an algorithm which decides this equivalence in time polynomial in the number of instructions executed and the number of registers. We implement the algorithm and demonstrate how the framework facilitates debugging.
Publisher
Association for Computing Machinery (ACM)
Subject
Electrical and Electronic Engineering,Computer Graphics and Computer-Aided Design,Computer Science Applications
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