System and Design Technology Co-optimization of Chiplet-based AI Accelerator with Machine Learning-Reference-Cited by-同舟云学术

System and Design Technology Co-optimization of Chiplet-based AI Accelerator with Machine Learning

Published:2023-06-05 Issue: Volume: Page:
ISSN:
Container-title:Proceedings of the Great Lakes Symposium on VLSI 2023
language:
Short-container-title:

Author:

Mishty Kaniz¹^ORCID,Sadi Mehdi¹^ORCID

Affiliation:

1. Auburn University, Auburn, AL, USA

Funder

National Science Foundation

Publisher

ACM

Link

https://dl.acm.org/doi/pdf/10.1145/3583781.3590233

Reference27 articles.

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3. Chen , F.C. et al. 2019. System on Integrated Chips (SoICTM) for 3D Heterogeneous Integration . In 2019 IEEE 69th Electronic Components and Technology Conference. Chen, F.C. et al. 2019. System on Integrated Chips (SoICTM) for 3D Heterogeneous Integration. In 2019 IEEE 69th Electronic Components and Technology Conference.

4. Coskun , Ayse et al . 2022 . Cross-Layer Co-Optimization of Network Design and Chiplet Placement in 2.5-D Systems. In 2020 IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS , Vol. 39 . Coskun, Ayse et al. 2022. Cross-Layer Co-Optimization of Network Design and Chiplet Placement in 2.5-D Systems. In 2020 IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, Vol. 39.

5. Peter I. Frazier. 2018. A Tutorial on Bayesian Optimization. arXiv:arXiv:1807.02811 Peter I. Frazier. 2018. A Tutorial on Bayesian Optimization. arXiv:arXiv:1807.02811