MCSim: A Multi-Core Cache Simulator Accelerated on a Resource-constrained FPGA-Reference-Cited by-同舟云学术

MCSim: A Multi-Core Cache Simulator Accelerated on a Resource-constrained FPGA

Published:2023-06-05 Issue: Volume: Page:
ISSN:
Container-title:Proceedings of the Great Lakes Symposium on VLSI 2023
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Author:

Shah Shivani¹^ORCID,Rao Nanditha P.¹^ORCID

Affiliation:

1. International Institute of Information Technology Bangalore, Bangalore, India

Publisher

ACM

Link

https://dl.acm.org/doi/pdf/10.1145/3583781.3590309

Reference9 articles.

1. Raul Martin Miguel A, Vega-Rodriguez, Francisco A, and Zarallo Gallardo . 2006 . Smpcache: Simulator for cache memory systems on symmetric multiprocessors . http://arco.unex.es/smpcache/ Retrieved May 10, 2021 from Raul Martin Miguel A, Vega-Rodriguez, Francisco A, and Zarallo Gallardo. 2006. Smpcache: Simulator for cache memory systems on symmetric multiprocessors. http://arco.unex.es/smpcache/ Retrieved May 10, 2021 from

2. Sniper

3. Jan Edler. 1998. Dinero IV trace-driven uniprocessor cache simulator. http://pages.cs.wisc.edu/ markhill/DineroIV/ Retrieved Feb 7 2022 from Jan Edler. 1998. Dinero IV trace-driven uniprocessor cache simulator. http://pages.cs.wisc.edu/ markhill/DineroIV/ Retrieved Feb 7 2022 from

4. Nathan Gober . 2017. Champsim. https://github.com/ChampSim/ Retrieved Mar 15, 2022 from Nathan Gober. 2017. Champsim. https://github.com/ChampSim/ Retrieved Mar 15, 2022 from

5. Sources of error in full-system simulation

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