Affiliation:
1. Princeton University, Princeton, NJ, USA
2. Nvidia, Santa Clara, CA, USA
Abstract
Industry is building larger, more complex, manycore processors on the back of strong institutional knowledge, but academic projects face difficulties in replicating that scale. To alleviate these difficulties and to develop and share knowledge, the community needs open architecture frameworks for simulation, synthesis, and software exploration which support extensibility, scalability, and configurability, alongside an established base of verification tools and supported software. In this paper we present OpenPiton, an open source framework for building scalable architecture research prototypes from 1 core to 500 million cores. OpenPiton is the world's first open source, general-purpose, multithreaded manycore processor and framework. OpenPiton leverages the industry hardened OpenSPARC T1 core with modifications and builds upon it with a scratch-built, scalable uncore creating a flexible, modern manycore design. In addition, OpenPiton provides synthesis and backend scripts for ASIC and FPGA to enable other researchers to bring their designs to implementation. OpenPiton provides a complete verification infrastructure of over 8000 tests, is supported by mature software tools, runs full-stack multiuser Debian Linux, and is written in industry standard Verilog. Multiple implementations of OpenPiton have been created including a taped-out 25-core implementation in IBM's 32nm process and multiple Xilinx FPGA prototypes.
Funder
Air Force Office of Scientific Research
Defense Advanced Research Projects Agency
National Science Foundation
Publisher
Association for Computing Machinery (ACM)
Reference86 articles.
1. Beri processor 'arcina' release 1. https://github.com/CTSRD-CHERI/beri. Accessed Jan. 2016. Beri processor 'arcina' release 1. https://github.com/CTSRD-CHERI/beri. Accessed Jan. 2016.
2. eXtensible Utah Multicore (xum). https://github.com/grantae/mips32r1_xum. Accessed Jan. 2016. eXtensible Utah Multicore (xum). https://github.com/grantae/mips32r1_xum. Accessed Jan. 2016.
3. Mips32 release 1. https://github.com/grantae/mips32r1_core. Accessed Jan. 2016. Mips32 release 1. https://github.com/grantae/mips32r1_core. Accessed Jan. 2016.
4. Zet processor. http://zet.aluzina.org/index.php/Zet_processor. Accessed Jan. 2016. Zet processor. http://zet.aluzina.org/index.php/Zet_processor. Accessed Jan. 2016.
5. Zylin cpu. https://github.com/zylin/zpu. Accessed Jan. 2016. Zylin cpu. https://github.com/zylin/zpu. Accessed Jan. 2016.
Cited by
10 articles.
订阅此论文施引文献
订阅此论文施引文献,注册后可以免费订阅5篇论文的施引文献,订阅后可以查看论文全部施引文献
1. A Hardware Security Evaluation Platform on RISC-V SoC;2024 IEEE International Test Conference in Asia (ITC-Asia);2024-08-18
2. Scratchy: A Class of Adaptable Architectures with Software-Managed Communication for Edge Streaming Applications;Lecture Notes in Computer Science;2024
3. Seizing the Bandwidth Scaling of On-Package Interconnect in a Post-Moore's Law World;Proceedings of the 37th International Conference on Supercomputing;2023-06-21
4. SMAPPIC: Scalable Multi-FPGA Architecture Prototype Platform in the Cloud;Proceedings of the 28th ACM International Conference on Architectural Support for Programming Languages and Operating Systems, Volume 2;2023-01-27
5. SEU Reliability Assessment Framework for COTS Many-core Processors;2022 International Conference on Microelectronics (ICM);2022-12-04