Synthesizing Formal Models of Hardware from RTL for Efficient Verification of Memory Model Implementations-Reference-Cited by-同舟云学术

Synthesizing Formal Models of Hardware from RTL for Efficient Verification of Memory Model Implementations

Published:2021-10-17 Issue: Volume: Page:
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Container-title:MICRO-54: 54th Annual IEEE/ACM International Symposium on Microarchitecture
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Author:

Hsiao Yao¹,Mulligan Dominic P.²,Nikoleris Nikos²,Petri Gustavo²,Trippel Caroline¹

Affiliation:

1. Stanford University, United States of America

2. Arm Research, United Kingdom

Funder

National Science Foundation

Publisher

ACM

Link

Reference46 articles.

3. Arm. 2013. Arm Architecture Reference Manual. Arm. 2013. Arm Architecture Reference Manual.

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