Twig: Profile-Guided BTB Prefetching for Data Center Applications-Reference-Cited by-同舟云学术

Twig: Profile-Guided BTB Prefetching for Data Center Applications

Published:2021-10-17 Issue: Volume: Page:
ISSN:
Container-title:MICRO-54: 54th Annual IEEE/ACM International Symposium on Microarchitecture
language:
Short-container-title:

Author:

Khan Tanvir Ahmed¹,Brown Nathan²,Sriraman Akshitha¹,Soundararajan Niranjan K³,Kumar Rakesh⁴,Devietti Joseph⁵,Subramoney Sreenivas³,Pokam Gilles A⁶,Litz Heiner⁷,Kasikci Baris¹

Affiliation:

1. University of Michigan, United States of America

2. University of Michigan

3. Intel Labs, India

4. Norwegian University of Science and Technology (NTNU), Norway

5. University of Pennsylvania, United States of America

6. Intel, United States of America

7. University of California, Santa Cruz, United States of America

Funder

Intel Corporation

NSF

Applications Driving Architectures (ADA) Research Center, a JUMP Center co-sponsored by SRC and DARPA

Publisher

ACM

Link

https://dl.acm.org/doi/pdf/10.1145/3466752.3480124

Reference90 articles.

1. [n. d.]. Adding Processor Trace support to Linux. https://lwn.net/Articles/648154/. [n. d.]. Adding Processor Trace support to Linux. https://lwn.net/Articles/648154/.

2. [n. d.]. Apache Cassandra. http://cassandra.apache.org/. [n. d.]. Apache Cassandra. http://cassandra.apache.org/.

3. [n. d.]. Apache kafka. https://kafka.apache.org/powered-by. [n. d.]. Apache kafka. https://kafka.apache.org/powered-by.

4. [n. d.]. Apache Tomcat. https://tomcat.apache.org/. [n. d.]. Apache Tomcat. https://tomcat.apache.org/.

5. [n. d.]. An Introduction to Last Branch Records. https://lwn.net/Articles/680985/. [n. d.]. An Introduction to Last Branch Records. https://lwn.net/Articles/680985/.

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