Interplay of Loop Unrolling and Multidimensional Memory Partitioning in HLS-Reference-Cited by-同舟云学术

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Interplay of Loop Unrolling and Multidimensional Memory Partitioning in HLS

Published:2015 Issue: Volume: Page:
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Container-title:Design, Automation & Test in Europe Conference & Exhibition (DATE), 2015
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Author:

Cilardo Alessandro,Gallo Luca

Publisher

IEEE Conference Publications

Cited by 11 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. Array Partitioning Method for Streaming Dataflow Optimization in High-level Synthesis;2024 2nd International Symposium of Electronics Design Automation (ISEDA);2024-05-10

2. Investigating the Effect of Hyper-Parameter Settings on Simulated Annealing-Based High-Level Synthesis Design Space Exploration;2024 IEEE 17th Dallas Circuits and Systems Conference (DCAS);2024-04-19

3. A Testing Program and Pragma Combination Selection Based Framework for High-Level Synthesis Tool Pragma-Related Bug Detection;IEEE Transactions on Software Engineering;2024-04

4. Fast and Inexpensive High-Level Synthesis Design Space Exploration: Machine Learning to the Rescue;IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems;2023-11

5. FPGA-based acceleration architecture for Apache Spark operators;CCF Transactions on High Performance Computing;2023-06-23

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