1. TCC: GPGPU Architecture for Instruction Decoder and Control Flow Error Detection;2024 27th International Symposium on Design & Diagnostics of Electronic Circuits & Systems (DDECS);2024-04-03
2. DDSR: An Online GPGPU Instruction Decoder Error Detecting and Correcting Architecture;2023 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT);2023-10-03
3. The IBM z13 multithreaded microprocessor;IBM Journal of Research and Development;2015-07
4. Efficient ASIC and FPGA Implementation of Binary-Coded Decimal Digit Multipliers;Circuits, Systems, and Signal Processing;2014-06-17
5. Performance innovation in the IBM zEnterprise 196 processor;IBM Journal of Research and Development;2012-01