Limited switch dynamic logic circuits for high-speed low-power circuit design
Author:
Publisher
IBM
Subject
General Computer Science
Link
http://xplorestaging.ieee.org/ielx5/5288520/5388720/05388724.pdf?arnumber=5388724
Cited by 8 articles. 订阅此论文施引文献 订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献
1. Design of Energy Efficient Magnitude Comparator Architecture using 8T XOR Gate;2022 3rd International Conference on Electronics and Sustainable Communication Systems (ICESC);2022-08-17
2. VLSI Implementation of a High Speed and Area efficient N-bit Digital CMOS Comparator;2021 Second International Conference on Smart Technologies in Computing, Electrical and Electronics (ICSTCEE);2021-12-16
3. Design of Arithmetic Logic Unit using Pseudo Dynamic Buffer based Domino Logic;Journal of Physics: Conference Series;2020-12-01
4. High‐speed and area‐efficient scalable N ‐bit digital comparator;IET Circuits, Devices & Systems;2020-03-10
5. Low-Power Near-Threshold 10T SRAM Bit Cells With Enhanced Data-Independent Read Port Leakage for Array Augmentation in 32-nm CMOS;IEEE Transactions on Circuits and Systems I: Regular Papers;2019-03
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