Advanced Thermal Study of Very High Power TSV Interposer and Interconnects for 28nm Technology FPGA

Abstract

TSV interposer has emerged as a good solution to provide high wiring density interconnections and improved electrical performance due to shorter interconnection from the die to substrate. Furthermore, silicon interposer minimizes CTE mismatch between the chip and copper filled TSV interposer resulting in high reliability micro bumps. This paper presents the thermal study of TSV interposer technology for a high-performance 28nm logic die that is mounted on a large silicon interposer with Cu through silicon via. A representative silicon interposer test chip with thousands of micro-bumps at 45um pitch has been fabricated. The silicon interposer is 100um thick, and is mounted on a 42.5mmx42.5mm substrate through 180um pitch C4 bumps. 3D thermal modeling and simulation for the packaged device with TSV interposer have been performed. Several DOEs have been constructed to optimize thermal interface material selection and to study the effect of high power and hot spots on underfill and solder bump material properties as well as the effect of bump pitch and underfill properties on the die junction temperatures. Furthermore, thermal behavior of 28nm technology monolithic FPGA was compared to the 3D TSV interposer FPGA package. Optimized passive thermal solution was recommended for this high power FPGA in order to cool down up to 100 Watt power.