A Small Feature-Sized Organic interposer for 2.1D Packaging Solutions

Author:

Romero Christian1,Lee Jeongho1,Oh Kyungseob1,Harr Kyoungmoo1,Kweon Youngdo1

Affiliation:

1. Advanced Circuit Interconnect Division, Samsung Electromechanics Co, Ltd, Suwon City, South Korea

Abstract

The continuing advancement of semiconductor devices steadily increase the number of global interconnects and higher I/O counts thus driving more the importance of smaller feature size interconnects. One of the most difficult technical challenge for interconnects involves new material development, however, it is believed that mitigation of the impact of size scaling such as its aspect ratio (thickness/width) and spacing could fill the gap for high dense packaging requirement brought by Moore's Law. The next generation substrate design rules require a process capability with less than 50um pitch to accommodate leading-edge mobile applications such as Wide I/O memory-Logic packaging integration. In this paper, we describe an organic interposer that is capable of providing high density interface between chips with large I/O counts therefore could be an attractive low-cost 2.1D packaging solution. Our concept can demonstrate ultra fine line interconnects with width/space below 5um with microvias having pitch below 50um which can be effective solution for high density routing. This feature enables the ICs to be attached directly to the substrate therefore eliminating the need for a silicon interposer needed in conventional 2.5D package architecture. Microvia formation using photo-imageable material is another key feature of our organic interposer offering favorable cost efficiency for designs requiring very large numbers of microvias. The buildup layers could be vertically connected by microvias with min. 10um diameter using this process. Aside from the simplicity in supply chain, the high density organic interposer has the potential to meet both power and bandwidth requirement therefore can be considered an incremental move from conventional system-in-package providing flexibility in performance and yield capacity that allows integration of advanced logic and memory devices. We will present our various feasibility results of electrical/mechanical performance obtained from our fabricated test vehicles.

Publisher

IMAPS - International Microelectronics Assembly and Packaging Society

Subject

General Medicine

Cited by 3 articles. 订阅此论文施引文献 订阅此论文施引文献,注册后可以免费订阅5篇论文的施引文献,订阅后可以查看论文全部施引文献

1. A Warpage Investigation for a Large Panel-sized Interposer with Embedded Dies;2024 IEEE 74th Electronic Components and Technology Conference (ECTC);2024-05-28

2. Artificial Intelligence (AI) based methodology to minimize asymmetric bare substrate warpage;2023 IEEE 73rd Electronic Components and Technology Conference (ECTC);2023-05

3. Advanced Flip Chip Packaging;Springer Series in Reliability Engineering;2023

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