500 kHz – 5 MHz Phase-Locked Loops in High-Temperature Silicon Carbide CMOS

Author:

Shepherd Paul1,Rahman Ashfaqur1,Ahmed Shamim1,Francis A Matt2,Holmes Jim2,Mantooth H. Alan1

Affiliation:

1. 1University of Arkansas Department of Electrical Engineering, 3217 Bell Engineering Center, Fayetteville, AR 72701

2. 2 Ozark Integrated Circuits, 700 West Research Center Blvd, Fayetteville, AR 72701

Abstract

Silicon Carbide (SiC) integrated circuits processes show promise for improved performance in high temperature, high radiation, and other extreme environments. The circuits described are the first implementations of phase-locked or delay-locked loops in SiC. The PLL utilizes a common charge-pump topology including a fully integrated passive loop filter, and were designed with a target maximum operating frequency of 5 MHz. Component blocks use novel topologies to optimize performance in a SiC CMOS process. Experimental results of both the complete PLL as well as the Phase Frequency Detector and Voltage Controlled Oscillator components are presented. Operation of the PLL at frequencies up to 1.5 MHz is demonstrated through test results of unpackaged die.

Publisher

IMAPS - International Microelectronics Assembly and Packaging Society

Cited by 2 articles. 订阅此论文施引文献 订阅此论文施引文献,注册后可以免费订阅5篇论文的施引文献,订阅后可以查看论文全部施引文献

1. A review of silicon carbide CMOS technology for harsh environments;Materials Science in Semiconductor Processing;2024-08

2. Design and Analysis of a Voltage Schmitt Trigger in 4H-SiC CMOS Technology;Lecture Notes in Electrical Engineering;2023-11-29

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