Three-Dimensional Wiring Fabricating Process of Cantilever-type Silicon Probe for Semiconductor Testing-Reference-Cited by-同舟云学术

Three-Dimensional Wiring Fabricating Process of Cantilever-type Silicon Probe for Semiconductor Testing

Published:2015 Issue:8 Volume:135 Page:349-354
ISSN:1341-8939
Container-title:IEEJ Transactions on Sensors and Micromachines
language:en
Short-container-title:IEEJ Trans. SM

Author:

Aono Takanori¹,Kanamaru Masatoshi¹,Kohno Ryuji¹,Hosogane Atsushi¹

Affiliation:

1. Hitachi, Ltd., Hitachi Research Laboratory

Publisher

Institute of Electrical Engineers of Japan (IEE Japan)

Subject

Electrical and Electronic Engineering,Mechanical Engineering

Link

https://www.jstage.jst.go.jp/article/ieejsmas/135/8/135_349/_pdf

Reference9 articles.

1. (1) W. R. Mann, F. L. Taber, P. W. Seitzer, and J. J. Broz : “THE LEADING EDGE OF PRODUCTION WAFER PROBE TEST TECHNOLOGY”, Proc. IEEE International Test Conference (ITC), pp. 1168-1195 (2004)

2. (2) S. Tanaka, S. Fujimoto, O. Ito, S.-H. Choe, and M. Esashi : “FABRICATION OF MICROPROBES ON A ULTARATHICK GLASS SUBSTRATE WITH NARROW-PITCH ELECTRICAL FEED THROUGHS FOR NEXT-GENERATION LSI BURN-IN TESTS”, TECHNICAL DIGEST MEMS2008, pp. 347-350 (2008)

3. (3) S. Asai, K. Kato, N. Nakazaki, and Y. Nakajima : “Probe Card with Probe Pins Grown by the Vapor-Liquid-Solid (VLS) Method”, IEEE Trans. on Components, Packaging, and Manufacturing Technology, Part A, Vol. 19, No. 2, pp. 258-267 (1996)

4. (4) M. Beiley, J. Leung, and S. S. Wong : “A Micromachined Array Probe Card - Fabrication Process”, IEEE Trans. on Components, Packaging, and Manufacturing Technology - Part B, Vol. 18, No. 1, pp. 179-183 (1995)

5. (5) M. Kanamaru, R. Kohno, Y. Endo, and A. Hosogane : “Development of Micro-Probe Substrate for LSI Testting”, Trans. IEEJ, Vol. 122-E, No. 9, pp. 440-446 (2002)