1. (1) T. Ohi, T. Horiguchi, T. Okuda, T. Kikunaga, and H. Matsumoto: “Analysis and measurement of chip current imbalance caused by the structure of Bus Bars in an IGBT module”, IEEE Industry Applications Conference, pp. 1775-1779 (1999)
2. (2) D. Bortis, J. Biela, and J. Kolar: “Active gate control for current balancing of parallel-connected IGBT modules in solid-state modulators”, IEEE Transactions on Plasma Science, Vol. 36, No. 5, pp. 2632-2637 (2008)
3. (3) M. Sasaki, W. T. Ng, and H. Nishio: “Dynamic gate resistance control for current balancing in parallel connected IGBTs”, Applied Power Electronics Conference and Exposition, pp. 244-249 (2013)
4. (4) Y. Onozawa, M. Otsuki, and Y. Seki: “Great Improvement in Turn-On Power Dissipation of IGBTs with an Extra Gate Charging Function”, International Symposium on Power Semiconductor Devices and ICs, pp. 207-210 (2005)
5. (5) Y. Onozawa, M. Otsuki, and Y. Seki: “Investigation of carrier streaming effect for the low spike fast IGBT turn-off”, International Symposium on Power Semiconductor Devices and ICs, 2006, pp. 173-176 (2006)