A Study on Effects of Deadtime in a Single-phase Multilevel Inverter Using Circuit Topology and the Modulation Method-Reference-Cited by-同舟云学术

A Study on Effects of Deadtime in a Single-phase Multilevel Inverter Using Circuit Topology and the Modulation Method

Published:2022-11-01 Issue:11 Volume:142 Page:762-774
ISSN:0913-6339
Container-title:IEEJ Transactions on Industry Applications
language:en
Short-container-title:IEEJ Trans. IA

Author:

Chiba Makoto¹,Natori Kenji¹,Sato Yukihiko¹

Affiliation:

1. Chiba University

Publisher

Institute of Electrical Engineers of Japan (IEE Japan)

Subject

Electrical and Electronic Engineering,Industrial and Manufacturing Engineering

Link

https://www.jstage.jst.go.jp/article/ieejias/142/11/142_762/_pdf

Reference17 articles.

1. (1) D. Leggate and R. J. Kerkman: “Pulse-Based Dead-Time Compensator for PWM Voltage Inverters”, IEEE Trans. Ind. Electron., Vol. 44, No. 2, pp. 191-197 (1997)

2. (2) L. Ben-Brahim: “The analysis and compensation of dead-time effects in three phase PWM inverters”, Industrial Electronics Society IECON 1998-24th Annual Conference of the IEEE, pp. 792-797 (1998)

3. (3) 電気学会半導体電力変換システム調査専門委員会：「パワーエレクトロニクス回路」, オーム社, pp. 202-205 (2000)

4. (4) J. K. Park, K. M. Cho, W. S. Oh, K. Sol, and C. G. In: “Analysis of the errors on the output voltage of inverter caused by switching dead times”, 2008 International Symposium on Power Electronics, Electrical Drives, Automation and Motion, pp. 987-991 (2008)

5. (5) J. Itoh, T. Fujii, T. Hoshino, A. Odaka, I. Sato, and D. Tanaka: “Analysis of Dead-Time Compensation Method Using Disturbance Observer for Vector Control”, IEEJ Trans. IA, Vol. 128, No. 8, pp. 1005-1012 (2008) (in Japanese)