Research on Fault Tolerant Processor using Dynamic Reconfiguration-Reference-Cited by-同舟云学术

Research on Fault Tolerant Processor using Dynamic Reconfiguration

Published:2019-02-01 Issue:2 Volume:139 Page:187-192
ISSN:0913-6339
Container-title:IEEJ Transactions on Industry Applications
language:en
Short-container-title:IEEJ Trans. IA

Author:

Ogido Seiya¹,Yamada Chikatoshi¹,Miyagi Kei¹,Ichikawa Shuichi²,Fujieda Naoki²

Affiliation:

1. National Institute of Technology, Okinawa College

2. Toyohashi University of Technology

Publisher

Institute of Electrical Engineers of Japan (IEE Japan)

Subject

Electrical and Electronic Engineering,Industrial and Manufacturing Engineering

Link

https://www.jstage.jst.go.jp/article/ieejias/139/2/139_187/_pdf

Reference10 articles.

1. (1) H. Kawai, Y. Yamaguchi, and M. Yasunaga: “Realization of the sound space environment for the radiation-tolerant space craft”, Proc. IEEE Conf. on Reconfigurable Computing and FPGA's, ReConFig 2006, pp. 198-205 (2006)

2. (2) K. Fujisawa, M. Amagasaki, M. Iida, M. Kuga, and T. Sueyoshi: “A study of run-time fault detection mechanism for fault-tolerant FPGAs”, IEICE Technical Report, Vol. 114, No. 223, pp. 13-18 (2014) (in Japanese)

3. (3) M. Amagasaki, K. Inoue, Q. Zhao, M. Kuga, and T. Sueyoshi: “Defect-robust FPGA architectures for intellectual property cores in system LSI”, Proc. 23rd Int. Conf. on Field programmable Logic and Applications (FPL2013), pp. 1-7 (2013)

4. (4) K. Inoue, M. Koga, M. Iida, M. Amagasaki, Y. Ichida, M. Saji, J. Iida, and T. Sueyoshi: “An Easily Testable Routing Architecture and Prototype Chip”, IEICE Trans. on Inf. & Syst., Vol. E95-D, No. 2, pp. 303-313 (2012)

5. (5) M. Amagasaki, Y. Nishitani, K. Inoue, M. Iida, M. Kuga, and T. Sueyoshi: “A Novel Detection and Recovery Techniques for Physical Defect in FPGA-IP Cores”, IEICE Trans. on Inf. & Syst., Vol. J96-D, No. 12, pp. 3019-3029 (2013) (in Japanese)