Design Technology of Stacked Type Chain PRAM

Author:

Kato Sho1,Watanabe Shigeyoshi1

Affiliation:

1. Department of Information Science, Shonan Institute of Technology

Publisher

Institute of Electrical Engineers of Japan (IEE Japan)

Subject

Electrical and Electronic Engineering

Reference22 articles.

1. (1) S. Kan et al. : “A 0.1um 1.8-V 256-Mb Phase-Change Random Access memory (PRAM) with 66-MHz synchronous burst-read operation”, IEEE J. Solid-State Circuits, Vol. 42, No. 1, pp. 210-218 (2007)

2. (2) W. Cho et al. : “A 0.18-um 3.0-V 64-Mb nonvolatile phase transition random access memory (PRAM)”, IEEE J. Solid-State Circuits, Vol. 40, No. 1, pp. 293-300 (2005)

3. (4) Y. Sasago et al. : “Phase-change memory driven by poly-Si MOS transistor with low cost and high-programing gigabyte-per-second throuput”, Symp. on VLSI tech., pp. 96-97 (2011)

4. (5) D. Takashima et al. : “High-density chain ferroelectric random-access memory (CFRAM)”, Symp. on VLSI Circuit., pp. 83-84 (1997)

Cited by 1 articles. 订阅此论文施引文献 订阅此论文施引文献,注册后可以免费订阅5篇论文的施引文献,订阅后可以查看论文全部施引文献

1. Proposal of Hierarchical Stacked Type Fe-FET NAND/NAND Array and its Application to Logic LSI;IEEJ Transactions on Electronics, Information and Systems;2017

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