Design Method of C-2C D/A Converter Using Integer Capacitance Ratio-Reference-Cited by-同舟云学术

Design Method of C-2C D/A Converter Using Integer Capacitance Ratio

Published:2020-02-01 Issue:2 Volume:140 Page:194-203
ISSN:0385-4221
Container-title:IEEJ Transactions on Electronics, Information and Systems
language:en
Short-container-title:IEEJ Trans.EIS

Author:

Sekine Satoshi¹,Matsuura Tatsuji²,Kishida Ryo²,Hyogo Akira²

Affiliation:

1. Department of Electrical Engineering, Graduate School of Science and Technology, Tokyo University of Science

2. Department of Electrical Engineering, Faculty of Science and Technology, Tokyo University of Science

Publisher

Institute of Electrical Engineers of Japan (IEE Japan)

Subject

Electrical and Electronic Engineering

Link

https://www.jstage.jst.go.jp/article/ieejeiss/140/2/140_194/_pdf

Reference17 articles.

1. (1) Y. S. Yee, L. M. Terman, and L. G. Heller : “A two-stage weighted capacitor network for D/A-A/D conversion”, IEEE J. Solid-State Circuits, Vol. 14, No. 4, pp. 778-781 (1979)

2. (2) S. P. Singh, A. Prabhakar, and A. B. Bhattcharyya : “C-2C Ladder-Based D/A Converters for PCM codecs”, IEEE J. Solid-State Circuits, Vol. SC-22, No. 6, pp. 1197-1200 (1987)

3. (3) L. Cong : “Pseudo C-2C Ladder-Based Data Converter Technique”, IEEE Trans. Circuits Syst. II, Analog Digit. Signal Process., Vol. 48, No. 10, pp. 927-929 (2001)

4. (4) E. Alpman, H. Lakdawala, L. R. Carley, and K. Soumyanath : “A 1.1V 50mW 2.5GS/s 7b Time-Interleaved C-2C SAR ADC in 45nm LP digital CMOS”, IEEE International Solid-State Circuits Conference - Digest of Technical Papers, San Francisco, CA, pp. 76-77, 77a (2009)

5. (5) J. Yang, T. L. Naing, and R. W. Brodersen : “A 1 GS/s 6 bit 6.7 mW Successive Approximation ADC Using Asynchronous Processing”, IEEE Journal of Solid-State Circuits, Vol. 45, No. 8, pp. 1469-1478 (2010)

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