A Study on Output Voltage of a Chaotic Neuron Model with Low Capacity
Author:
Affiliation:
1. College of Science & Technology, Nihon University
2. Graduate School of Science & Technology, Nihon University
Publisher
Institute of Electrical Engineers of Japan (IEE Japan)
Subject
Electrical and Electronic Engineering
Link
https://www.jstage.jst.go.jp/article/ieejeiss/138/7/138_766/_pdf
Reference25 articles.
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2. (5) K. Sasaki, T. Morie, S. Ii, and A. Iwata : “Fast associative memory using spiking Hopfield networks based on pulse timing processing”, IEICE Technical Report, NC2002-81, pp. 91-95 (2002) (in Japanese)
3. (6) I. Obana : “Chaotic Firing Property of a Neuron Represented by an Electoronic Circuit”, IEEJ Trans. EIS, Vol. 116, No. 12, pp. 1378-1381 (1996) (in Japanese)
4. (7) T. Matsuzaki and M. Nakagawa : “A Bipolar Logistic Chaos Neuron and Its Hardware Implementation”, The IEIECE Tran. A, Vol. J85-A, No. 5, pp. 537-547 (2002) (in Japanese)
5. (8) H. Hayashi, S. Ishizuka, M. Ohta, and K. Hirakawa : “Chaos in Excitable Lipid Membranes”, Phys. Lett., 88A 435 (1982)
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