A Hardware Chaotic Neural Network with Gap Junction Models
Author:
Affiliation:
1. Postdoctoral Course in Electronic Engineering, Graduate School of Science and Engineering, Nihon University
2. Electronic Engineering, Science and Technology, Nihon University
Publisher
Institute of Electrical Engineers of Japan (IEE Japan)
Link
https://www.jstage.jst.go.jp/article/ieejeiss/144/7/144_580/_pdf
Reference13 articles.
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2. (2) Y. Sakemi, S. Nobukawa, T. Matsuki, T Morie, and K. Aihara : “Learning Reservoir Dynamics with Temporal Self-Modulation”, arXiv preprint arXiv:2301.09235 (2023)
3. (3) S. T. Chandrasekaran, A. P. Kuruvila, K. Basu, and A. Sanyal : “Real-Time Hardware-Based Malware and Micro-Architectural Attack Detection Utilizing CMOS Reservoir Computing”, IEEE Trans Circuits Syst II Express Briefs, Vol. 69, No. 2, pp. 349-353 (2022)
4. (4) A. Morán, V. Canals, F. Galan-Prado, C. F. Frasser, D. Radhakrishnan, S. Safavi, and J. L. Rosselló : “Hardware-Optimized Reservoir Computing System for Edge Intelligence Applications”, Cognitive Computation, Vol. 15, pp. 1461-1469 (2023)
5. (5) K. Saeki, Y. Sekine, and K. Aihara : “Chaos in a Pulse-type Hardware Neuron Model”, pp. 277-295, World Scientific Publishing Co. Singapore (2002)
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