Double-Mapping-Based SVM Method for Balancing DC-Link Input Voltages of a Five-Level Inverter
Author:
Affiliation:
1. Department of Electrical Engineering, Doshisha University
Publisher
Institute of Electrical Engineers of Japan (IEE Japan)
Subject
Electrical and Electronic Engineering
Link
https://www.jstage.jst.go.jp/article/ieejeiss/138/11/138_1319/_pdf
Reference19 articles.
1. (1) A. Nabae, I. Takahashi, and H. Akagi: “A new neutral-point-clamped PWM inverter”, IEEE Transactions on Industry Applications, Vol. IA-17, No. 5, pp. 518-523 (1981)
2. (2) N. S. Choi, J. G. Cho, and G. H. Cho: “A general circuit topology of multilevel inverter”, IEEE Power Electronics Specialists Conference(PESC), pp. 96-103 (1991)
3. (3) N. Hatti, Y. Kondo, and H. Akagi: “Five-level diode-clamped pwm converters connected back-to-back for motor drives”, IEEE Transactions on Industry Applications, Vol. 44, No. 4, pp. 1268-1276 (2008)
4. (4) K. Sano and H. Fujita: “Voltage-balancing circuit based on a resonant switched-capacitor converter for multilevel inverters”, IEEE Transactions on Power Electronics, Vol. 44, pp. 1768-1776 (2008)
5. (6) K. Hasegawa and H. Akagi: “A new dc-voltage-balancing circuit including a single coupled inductor for a five-level diode-clamped pwm inverter”, IEEE Transactions on Power Electronics, Vol. 47, pp. 841-852 (2011)
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