Simulating of charge build-up in irradiated MOS/SOI transistors-Reference-Cited by-同舟云学术

Simulating of charge build-up in irradiated MOS/SOI transistors

Published:2020-01-07 Issue:4 Volume:55 Page:498-504
ISSN:2524-2415
Container-title:Proceedings of the National Academy of Sciences of Belarus. Physics and Mathematics Series
language:
Short-container-title:Vescì Akademìì navuk Belarusì. Seryâ fizika-matematyčnyh navuk

Author:

Ogorodnikov D. A.¹,Lastovskii S. B.¹,Bogatyrev Yu. V.¹

Affiliation:

1. SSPA “Scientific-Practical Materials Research Centre of NAS of Belarus”

Abstract

The charge build-up in the interface of silicon / buried oxide in n-channel MOS/SOI transistors depending on their geometric parameters and electrical modes during ionizing irradiation is calculated with the use of the software Silvaco. It is shown that the electrical mode is most “harsh”, when during irradiation the voltage of +5 V is applied to drain and source electrodes and 0 V is applied to substrate, gate and channel feeding. The amount of the built-up charge can be substantially reduced by applying a negative bias to the substrate and by decreasing the thickness of the buried oxide layer.

Publisher

Publishing House Belorusskaya Nauka

Subject

Computational Theory and Mathematics,General Physics and Astronomy,General Mathematics

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