Hyper redundancy for super reliable FPGAs

Abstract

The subject of the research presented in the article is hyper-redundant elements and FPGA devices that can be used in highly reliable digital systems (HRDS). The current work develops hyper-reliable logic elements, memory elements, and buffer elements for HRDS based on FPGAs, their simulation, and reliability assessment. Objective: to develop fault-tolerant logical elements of LUT for one, two, and three variables. Develop fault-tolerant static random access memory, D – flip-flop, and buffer element. To do a simulation in NI Multisim to validate performance and estimate complexity and power consumption. Derive formulas for assessing the reliability of the developed elements and devices and build graphs of comparison with known methods of triple modular redundancy. Methods used the introduction of redundancy in transistor level, simulation methods in Multisim, mathematical estimations of transistor number, reliability calculations. The following results were obtained: when introducing redundancy at the transistor level and using series-parallel circuits, it is necessary to at least quadruple the number of transistors. Passive-fail-safe elements and devices have been developed that can withstand one, two, and three transistor failures (errors). An assessment of their effectiveness has been conducted, showing their preference over the majority reservation. Conclusions. The synthesis and analysis of passive-fault-tolerant circuits with an ocean of redundancy, which ensures the preservation of a logical function for a given number of failures (from one to three), have been conducted. The costs are more than to maintain functional completeness in the method previously proposed by the author, but they are worth it. Despite the significantly greater redundancy compared to majority redundancy, power consumption turned out to be lower with an insignificant increase in latency. The proposed hyper-fault-tolerant FPGAs are advisable to use in critical application systems when maintenance is impossible. In the future, it is advisable to consider the issue of redundancy at the transistor level using bridge circuits.