Mask configurable readout circuit architecture for an ultra-high-resolution CMOS image sensor

Abstract

As the level of detail in today’s images increases, so does the demand for resolution. Due to the necessity of mask stitching technology for full exposure of large array chips, we propose a mask configurable readout circuit architecture, which is suitable for large array structures. However, the stitchable readout circuit architecture has some non-ideal effects: row driver function failure and the column non-consistency problem. In our design, we solve the problem of column non-consistency after stitching. At the same time, we changed the signal transmission structure in order to avoid the row driver function failure caused by the mask stitching. In this paper, a prototype 2130 × 2130 CMOS image sensor is fabricated in 0.11 µm CMOS technology. The chip can capture images at 20 fps and reduce fixed pattern noise (FPN) from 3.5% to 1.5% through correction techniques. The architecture proposed in this paper is suitable for large array image sensors.