Fabrication of a self-aligned multi-waveguide-layer passive Si3N4/SiO2 photonic integrated circuit for a 3-D optical phased array device

Abstract

Most traditional PICs (photonics integrated circuits) are based on a single-waveguide-layer configuration, which takes advantage of the mature fabrication process from the EIC (electronic integrated circuits) industry; but in the meantime, this configuration also limits the performance of PICs in applications such as OPA (optical phased array) devices. We have proposed a multi-waveguide-layer 3-D (3 dimensional) OPA device and demonstrated its unique advantage in broadband high efficiency. In this paper, we present the fabrication process of the proposed 3-D OPA in detail. By developing the fabrication process with a single lithography step, we address the two potential issues in a multi-waveguide-layer PIC: the alignment between layers; and the accurate spacing control between layers. The detailed considerations of processes are also elaborated, especially in the PR (photoresist) exposure and etching.