Experimental demonstration of a 160 Gbit/s 3D-integrated silicon photonics receiver with 1.2-pJ/bit power consumption

Abstract

By using the flip-chip bonding technology, a high performances 3D-integrated silicon photonics receiver is demonstrated. The receiver consists of a high-speed germanium-silicon (Ge-Si) photodetector (PD) and a commercial linear transimpedance amplifiers (TIA). The overall 3 dB bandwidth of the receiver is around 38 GHz with appropriate gain. Based on this 3D-integrated receiver, the 56, 64, 90, 100 Gbit/s non-return-to-zero (NRZ) and 112, 128 Gbit/s four-level pulse amplitude (PAM-4) modulation clear openings of eye diagrams are experimentally obtained. The sensitivities of -10, -5.2 dBm and -6.6, -2.7 dBm were obtained for 112 Gbit/s NRZ and 160 Gbit/s PAM-4 at hard-decision forward err correction (HD-FEC,3.8 × 10−3) and KP4 forward err correction (KP4-FEC,2 × 10−4) threshold, respectively. Additionally, the lowest power consumption of this receiver is about 1.2 pJ/bit, which implies its huge potential for short-reach data center applications.