Optical configuration acceleration on a new optically reconfigurable gate array very large scale integration using a negative logic implementation

Author:

Moriwaki Retsu,Watanabe Minoru

Funder

Ministry of Internal Affairs and Communications of Japan

Publisher

The Optical Society

Subject

Atomic and Molecular Physics, and Optics,Engineering (miscellaneous),Electrical and Electronic Engineering

Reference11 articles.

1. A 90 nm high volume manufacturing logic technology featuring novel 45 nm gate length strained silicon CMOS transistors;Ghani,2003

2. Strained FDSOI CMOS technology scalability down to 2.5 nm film thickness and 18 nm gate length with a TiN/HfO2 gate stack;Barral,2007

3. Capacitive coupling of data and power for 3D silicon-on-insulator VLSI;Culurciello,2005

4. 3D-Vias aware quadratic placement for 3D VLSI circuits;Hentschke,2007

5. Design and Demonstration of a Fully Integrated Multi-Technology FPGA: A Reconfigurable Architecture for Photonic and Other Multi-Technology Applications

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3. High total-ionizing-dose tolerance field programmable gate array;2018 IEEE International Symposium on Circuits and Systems (ISCAS);2018-05

4. Parallel light configuration that increases the radiation tolerance of integrated circuits;Optics Express;2017-10-30

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