Enabling Scalable Disintegrated Computing Systems With AWGR-Based 25D Interconnection Networks-Reference-Cited by-同舟云学术

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Enabling Scalable Disintegrated Computing Systems With AWGR-Based 25D Interconnection Networks

Published:2019-06-13 Issue:7 Volume:11 Page:333
ISSN:1943-0620
Container-title:Journal of Optical Communications and Networking
language:en
Short-container-title:J. Opt. Commun. Netw.

Author:

Fotouhi Pouya,Werner Sebastian,Proietti Roberto^ORCID,Xiao Xian,Ben Yoo S. J.

Publisher

The Optical Society

Subject

Computer Networks and Communications

Reference57 articles.

1. NoC architectures for silicon interposer systems: Why pay for more wires when you can get them (from your interposer) for free?;Jerger,2014

2. Enabling interposer-based disintegration of multi-core processors;Kannan,2015

3. AMD’s next generation GPU and high bandwidth memory architecture: FURY;Macri,2015

4. Interconnect-memory challenges for multi-chip, silicon interposer systems;Loh,2015

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1. Silicon Photonic 2.5D Interposer Networks for Overcoming Communication Bottlenecks in Scale-out Machine Learning Hardware Accelerators;2024 IEEE 42nd VLSI Test Symposium (VTS);2024-04-22

2. Machine Learning Accelerators in 2.5D Chiplet Platforms with Silicon Photonics;2023 Design, Automation & Test in Europe Conference & Exhibition (DATE);2023-04

3. ReSiPI;Proceedings of the 41st IEEE/ACM International Conference on Computer-Aided Design;2022-10-30

4. On the routing and scalability of MZI-based optical Beneš interconnects;Nano Communication Networks;2021-03

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