1. Alameldeen A., and Wood D., February 2003. Variability in architectural simulations of multithreaded workloads. In Proceedings of the Ninth International Symposium on High-Performance Computer Architecture (HPCA), pp. 7–18.
2. Arvind, Asanovic K., Chiou D., Hoe J.C., Kozyrakis C., Lu S. -L., Oskin M., Patterson D., Rabaey J., and Wawrzynek J., 2005. RAMP: Research accelerator for multiple processors—a community vision for a shared experimental parallel HW/SW platform. Tech. rep., University of California, Berkeley.
3. SimpleScalar: An infrastructure for computer system modeling;Austin;IEEE Computer,2002
4. Barr K. C., and Asanovic K., March 2006. Branch trace compression for snapshot-based simulation. In Proceedings of the International Symposium on Performance Analysis of Systems and Software (ISPASS), pp. 25–36.
5. Barr K. C., Pan H., Zhang M., and Asanovic K., March 2005. Accelerating multiprocessor simulation with a memory timestamp record. In Proceedings of the 2005 IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS), pp. 66–77.