Low-level implementation of the SISC protocol for thread-level speculation on a multi-core architecture

Author:

Radulović Milan B.,Girbal Sylvain,Tomašević Milo V.

Publisher

Elsevier BV

Subject

Artificial Intelligence,Computer Graphics and Computer-Aided Design,Computer Networks and Communications,Hardware and Architecture,Theoretical Computer Science,Software

Reference47 articles.

1. Radulović, M., PhD thesis, A Proposal of Support for Thread-Level Speculation in CMPs, School of Electrical Engineering, University of Belgrade, Serbia, Submitted in November 2014, defended on 20th of March 2015.

2. Chip multiprocessor architecture: techniques to improve throughput and latency;Olukotun,2007

3. D.W. Wall, Limits of Instruction-Level Parallelism, Digital Western Research laboratory, WRL Research Report 93/6, November 1993.

4. Cramming more components onto integrated circuits;Moore;Electronics,1965

5. The International Technology Roadmap for Semiconductors 2.0: 2015, http://www.itrs2.net/, (accessed 15.05.2016).

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