An automatic cell pattern generation system for CMOS transistor-pair array LSI

Author:

Miyashita Hiroshi,Adachi Tohru,Ueda Kazuhiro

Publisher

Elsevier BV

Subject

Electrical and Electronic Engineering,Hardware and Architecture,Software

Reference16 articles.

1. On the ordening of connections for automatic wire routing;Abel;IEEE Trans. on Computers,1972

2. Hierarchical top-down layout design method for VLSI chip;Adachi,1982

3. On the probability of success in a routing process;Agrawal;Proc. IEEE,1976

4. Experiments with a density router for PC cards;Agrawal;IEEE Trans. Comput.,1979

5. Design Automation of Digital Systems;Akers,1972

Cited by 3 articles. 订阅此论文施引文献 订阅此论文施引文献,注册后可以免费订阅5篇论文的施引文献,订阅后可以查看论文全部施引文献

1. Placement algorithm for the optimal synthesized design of CMOS logic cells;International Journal of Electronics;1991-05

2. Layout optimization of static CMOS functional cells;IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems;1990-07

3. Optimal Chaining of CMOS Transistors in a Functional Cell;IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems;1987-09

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