Boolean satisfiability and equivalence checking using general Binary Decision Diagrams-Reference-Cited by-同舟云学术

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Boolean satisfiability and equivalence checking using general Binary Decision Diagrams

Published:1992-05 Issue:1 Volume:13 Page:1-16
ISSN:0167-9260
Container-title:Integration
language:en
Short-container-title:Integration

Author:

Ashar Pranav,Ghosh Abhijit,Devadas Srinivas

Publisher

Elsevier BV

Subject

Electrical and Electronic Engineering,Hardware and Architecture,Software

Reference14 articles.

1. Ordered binary decision diagrams and circuit structure;Berman,1989

2. Efficient implementation of a BDD package;Brace,1990

3. MIS: a multiple-level logic optimization system;Brayton;IEEE Trans. Computer-Aided Design,1987

4. Logic Minimization Algorithms for VLSI Synthesis;Brayton,1984

5. Graph-based algorithms for Boolean function manipulation;Bryant;IEEE Trans. Computers,1986

Cited by 8 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. Enhancing active model learning with equivalence checking using simulation relations;Formal Methods in System Design;2023-08-06

2. The Multi-SAT algorithm;Discrete Applied Mathematics;1999-10

3. On optimizing the satisfiability (SAT) problem;Journal of Computer Science and Technology;1999-01

4. Algorithms for the Satisfiability (SAT) Problem;Handbook of Combinatorial Optimization;1999

5. Parallel Algorithms for Satisfiability (SAT) Testing;The IMA Volumes in Mathematics and its Applications;1999

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