Massive parallelism in multi-level simulation of VLSI circuits-Reference-Cited by-同舟云学术

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Massive parallelism in multi-level simulation of VLSI circuits

Published:1992-12 Issue:2 Volume:14 Page:145-171
ISSN:0167-9260
Container-title:Integration
language:en
Short-container-title:Integration

Author:

De Gloria A.,Faraboschi P.

Publisher

Elsevier BV

Subject

Electrical and Electronic Engineering,Hardware and Architecture,Software

Reference23 articles.

1. Chip-Level Modeling with VHDL;Armstrong,1989

2. Hardware Accelerators for Electrical CAD;Ambler,1987

3. An empirical study of on-chip parallelism;Bailey,1988

4. A survey of hardware accelerators used in computer-aided design;Blank;IEEE Design & Test of Computers,1984

5. A class of min-cut placement algorithm;Breuer,1977

Cited by 1 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. A new modeling technique for mixed-mode simulation of CMOS circuits;Integration;1997-08

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