1. Considering timing constraints in synthesis from behavioral description;Camposano,1986
2. Retiming and resynthesis: Optimizing sequential networks with combinational techniques;Malik;IEEE Transactions on CAD/ICAS,1991
3. State assignment of controllers for optimal area implementation;Saucier,1990
4. Rescheduling for cycle time by reverse engineering;Wolf,1990
5. An efficient microcode compiler for custom DSP-processors;Goosens,1987