A hierarchy preserving hierarchical bottom-up 2-layer wiring algorithm with respect to via minimization-Reference-Cited by-同舟云学术

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A hierarchy preserving hierarchical bottom-up 2-layer wiring algorithm with respect to via minimization

Published:1993-07 Issue:1 Volume:15 Page:73-95
ISSN:0167-9260
Container-title:Integration
language:en
Short-container-title:Integration

Author:

Molitor Paul

Publisher

Elsevier BV

Subject

Electrical and Electronic Engineering,Hardware and Architecture,Software

Reference39 articles.

1. An easily testable optimal time VLSI-multiplier;Becker;Acta Informatica,1987

2. A graphical system for hierarchical specifications and checkups of VLSI circuits;Becker,1990

3. Hierarchical design based on a calculus of nets;Becker,1987

4. Stretching a knockknee layout for multilayer wiring;Brady;IEEE Transactions on Computers,1990

5. Ein grafisches Eingabesystem für CADIC;Burch,1988

Cited by 2 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. Conjugate conflict continuation graphs for multi-layer constrained via minimization;Information Sciences;2007-06

2. Knowledge-based genetic algorithm for layer assignment;Proceedings 24th Australian Computer Science Conference. ACSC 2001

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