HOP: A process model for synchronous hardware; semantics and experiments in process composition-Reference-Cited by-同舟云学术

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HOP: A process model for synchronous hardware; semantics and experiments in process composition

Published:1989-12 Issue:3 Volume:8 Page:209-247
ISSN:0167-9260
Container-title:Integration
language:en
Short-container-title:Integration

Author:

Gopalakrishnan Ganesh C.,Fujimoto Richard M.,Akella Venkatesh,Mani Narayana S.

Publisher

Elsevier BV

Subject

Electrical and Electronic Engineering,Hardware and Architecture,Software

Reference42 articles.

1. A micro assembler for the TI 74AS890 micro sequencer;Akella,1988

2. Compiling path expressions into VLSI circuits;Anantharaman,1985

3. Instruction set processor specifications (ISPS): The notation and its applications;Barbacci;IEEE Trans. Comput.,1981

4. The ESTEREL synchronous programming language and its mathematical semantics;Berry,1984

5. Automatic verification of sequential circuits using temporal logic;Browne,1985

Cited by 5 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. Verilog HDL Simulator Technology: A Survey;Journal of Electronic Testing;2014-05-23

2. Decomposition of Sequential Behavior Using Interface Specification and Complementation;VLSI Design;1995-01-01

3. Automatic Synthesis of Sequential Synchronizations**This work was supported, in part, by the National Science Foundation under the grants numbered MIP87-07067, DCR85-21947, and MIP89-21842.;Computer Hardware Description Languages and their Applications;1993

4. Toward a Basis for Protocol Specification and Process Decomposition ††This research was supported in part by the National Science Foundation under grants numbered MIP 8921842 and MIP 9208745.;Computer Hardware Description Languages and their Applications;1993

5. Hierarchical Action Refinement: A Methodology for Compiling Asynchronous Circuits from a Concurrent HDL;Computer Hardware Description Languages and their Applications;1991

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