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New algorithms for increased efficiency in hierarchical design rule checking

  • Published:1987-12 Issue:3-4 Volume:5 Page:319-336
  • ISSN:0167-9260
  • Container-title:Integration
  • language:en
  • Short-container-title:Integration

Author:

Hedenstierna Nils,Jeppson Kjell O.

Publisher

Elsevier BV

Subject

Electrical and Electronic Engineering,Hardware and Architecture,Software

Reference12 articles.

1. A hierarchical design-rule checking algorithm;Whitney;Lambda Magazine,1981

2. A constrained design methodology for VLSI;Tucker;VSLI Design,1982

3. Magic's incremental design-rule checker;Taylor,1984

4. Exploitation of hierarchy in analyses of integrated circuit artwork;Newell;IEEE Trans. CAD Integr. Circuits Systs.,1982

5. Hierarchical analysis of IC artwork with user defined abstraction rules;Scheffer,1985

Cited by 8 articles. 订阅此论文施引文献 订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. The halo algorithm-an algorithm for hierarchical design of rule checking of VLSI circuits;IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems;1993

2. Formal definitions of edge-based geometric design rules;IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems;1993

3. Designing a complementary design rule checker based on a binary balanced quad list quad tree;IEE Proceedings E Computers and Digital Techniques;1992

4. Using a multiple storage quad tree on a hierarchical VLSI compaction scheme;IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems;1990-05

5. New algorithms based on a multiple storage quadtree for hierarchical compaction of VLSI mask layout;Computer-Aided Design;1990-03
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