The instruction systolic array — a parallel architecture for VLSI-Reference-Cited by-同舟云学术

登录注册会员服务联系我们

The instruction systolic array — a parallel architecture for VLSI

Published:1986-03 Issue:1 Volume:4 Page:65-74
ISSN:0167-9260
Container-title:Integration
language:en
Short-container-title:Integration

Author:

Lang Hans-Werner

Publisher

Elsevier BV

Subject

Electrical and Electronic Engineering,Hardware and Architecture,Software

Reference13 articles.

1. Programmable systolic array;Chang;IEEE Comcon,1982

2. Systolic algorithms for running order statistics in signal and image processing;Fisher,1981

3. The design of special-purpose VLSI chips;Foster;IEEE Computer,1980

4. Direct VLSI implementation of combinatorial algorithms;Guibas,1979

Cited by 23 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. An area-efficient bit-serial integer and GF(2n) multiplier;Microelectronic Engineering;2007-02

2. A bit-serial floating-point unit for a massively parallel system on a chip;Parallel Algorithms and Applications;2004-06

3. A hybrid architecture for bioinformatics;Future Generation Computer Systems;2002-05

4. Scanning Biosequence Databases on a Hybrid Parallel Architecture;Euro-Par 2001 Parallel Processing;2001

5. Protein Sequence Comparison on the Instruction Systolic Array;Lecture Notes in Computer Science;2001

同舟云学术

1.学者识别学者识别

2.学术分析学术分析

3.人才评估人才评估

"同舟云学术"是以全球学者为主线，采集、加工和组织学术论文而形成的新型学术文献查询和分析系统，可以对全球学者进行文献检索和人才价值评估。用户可以通过关注某些学科领域的顶尖人物而持续追踪该领域的学科进展和研究前沿。经过近期的数据扩容，当前同舟云学术共收录了国内外主流学术期刊6万余种，收集的期刊论文及会议论文总量共计约1.5亿篇，并以每天添加12000余篇中外论文的速度递增。我们也可以为用户提供个性化、定制化的学者数据。欢迎来电咨询！咨询电话：010-8811{复制后删除}0370

www.globalauthorid.com

TOP