1. An O(N log N) algorithm for Boolean mask operations;Lauther,1981
2. Hardware acceleration for layout verification;Macomber;VLSI Design,1985
3. A hierarchical approach for layout versus circuit consistency check;Chao,1980
4. Exploitation of Hierarchy in Analyses of Integrated Circuit Artwork;Newell;IEEE Trans. CAD of Integrated Circuits and Systems, CAD-1,1982
5. Hierarchical circuit extraction with detailed parasitic capacitance;Tarolli,1983