Simulation and verification of void transfer patterning (VTP) technique for nm-scale features-Reference-Cited by-同舟云学术

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Simulation and verification of void transfer patterning (VTP) technique for nm-scale features

Published:2011-01 Issue:1 Volume:88 Page:53-59
ISSN:0167-9317
Container-title:Microelectronic Engineering
language:en
Short-container-title:Microelectronic Engineering

Author:

Josan Guriqbal Singh,Devasia Archana,Rommel Sean,Kurinec Santosh K.

Publisher

Elsevier BV

Subject

Electrical and Electronic Engineering,Surfaces, Coatings and Films,Condensed Matter Physics,Atomic and Molecular Physics, and Optics,Electronic, Optical and Magnetic Materials

Reference13 articles.

1. X‐ray lithography — A review and assessment of future applications

2. Maskless deposition of gold patterns on silicon

3. A spacer patterning technology for nanoscale CMOS

4. Patterning sub-30-nm MOSFET gate with i-line lithography

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