A fabrication process for self-connected horizontal SiGe nanowires-Reference-Cited by-同舟云学术

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A fabrication process for self-connected horizontal SiGe nanowires

Published:2020-02 Issue: Volume:220 Page:111150
ISSN:0167-9317
Container-title:Microelectronic Engineering
language:en
Short-container-title:Microelectronic Engineering

Author:

Merhej M.,Ecoffey S.,Sadani B.,Lee–Sang B.,Baron T.,David S.,Drouin D.,Salem B.^ORCID

Publisher

Elsevier BV

Subject

Electrical and Electronic Engineering,Surfaces, Coatings and Films,Condensed Matter Physics,Atomic and Molecular Physics, and Optics,Electronic, Optical and Magnetic Materials

Reference22 articles.

1. Monolithic 3D Integration: A Path from Concept to Reality;Shulaker,2015

2. A 0.9 pJ/bit, 12.8 GByte/s wide IO Memory Interface in a 3D-IC NoC-based MPSoC, VLSI Technology (VLSIT) Symposium on;Dutoit,2013

3. A review of 3-D packaging technology;Al-sarawi;IEEE Trans. Components Packag. Manuf. Technol. Part B.,1998

4. Future system-on-silicon LSI chips;Koyanagi;IEEE Micro.,1998

5. Monolithic 3D chip integrated with 500ns NVM, 3ps logic circuits and SRAM;Shen,2013

Cited by 1 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. Study of the rate of degradation of permalloy nanowires;Surface and Coatings Technology;2020-05

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