Author:
Alam Naushad,Anand Bulusu,Dasgupta S.
Subject
Electrical and Electronic Engineering,Surfaces, Coatings and Films,Safety, Risk, Reliability and Quality,Condensed Matter Physics,Atomic and Molecular Physics, and Optics,Electronic, Optical and Magnetic Materials
Reference27 articles.
1. Shahidi GG. Design-technology interaction for post-32 nm node CMOS technologies. In: Symposium on VLSI technology; 2010. p. 143–4.
2. Mobility enhancement technology for scaling of CMOS devices: overview and status;Song;J Electron Mater,2011
3. PMOSFET With 200% mobility enhancement induced by multiple stressors;Washington;IEEE Electron Dev Lett,2006
4. A 90nm high volume manufacturing logic technology featuring novel 45nm gate length strained silicon CMOS transistors;Ghani;IEDM Tech Dig,2003
5. Hornung B, Khamankar R, Niimi H, Goodwin M, Robertson L, Miles D, Kirkpatrick B, AlShareef H, Varghese A, Bevan M, Nicollian P, Chidambaram PR, Chakravarthi S, Gurba A, Zhang X, Blatchford J, Smith B, Lu JP, Deloach J, Rathsack B, Bowen C, Thakar G, Machala C, Grider T. A high performance 90nm logic technology with a 37nm gate length, dual plasma nitrided gate dielectric and differential offset spacer. In: Symposium on VLSI technology; 2003. p. 85–6.
Cited by
3 articles.
订阅此论文施引文献
订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献