A 3-D Circuit Model to evaluate CDM performance of ICs-Reference-Cited by-同舟云学术

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A 3-D Circuit Model to evaluate CDM performance of ICs

Published:2005-09 Issue:9-11 Volume:45 Page:1425-1429
ISSN:0026-2714
Container-title:Microelectronics Reliability
language:en
Short-container-title:Microelectronics Reliability

Author:

Sowariraj M.S.B.,Smedes Theo,de Jong Peter C.,Salm Cora,Mouthaan Ton,Kuper Fred G

Publisher

Elsevier BV

Subject

Electrical and Electronic Engineering,Surfaces, Coatings and Films,Safety, Risk, Reliability and Quality,Condensed Matter Physics,Atomic and Molecular Physics, and Optics,Electronic, Optical and Magnetic Materials

Reference6 articles.

1. Role of package parasitics and substrate resistance on the Charged Device Model (CDM) failure levels –An explanation and die protection strategy

2. Modular approach of a high current MOS compact model for circuit-level ESD simulation including transient gate-coupling behaviour

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