A high fault coverage test approach for communication channels in network on chip-Reference-Cited by-同舟云学术

A high fault coverage test approach for communication channels in network on chip

Published:2017-08 Issue: Volume:75 Page:178-186
ISSN:0026-2714
Container-title:Microelectronics Reliability
language:en
Short-container-title:Microelectronics Reliability

Author:

Aghaei Babak^ORCID

Publisher

Elsevier BV

Subject

Electrical and Electronic Engineering,Surfaces, Coatings and Films,Safety, Risk, Reliability and Quality,Condensed Matter Physics,Atomic and Molecular Physics, and Optics,Electronic, Optical and Magnetic Materials

Reference51 articles.

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2. Networks on chip: a new paradigm for systems on chip design;De Micheli,2002

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4. On-chip networks: a scalable, communication-centric embedded system design paradigm;Henkel,2004

5. Reliability, Availability and Serviceability of Networks-on-chip;Cota,2011

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1. Towards Task Mapping Approaches in Network on Chips: A Comprehensive Survey;2023-07-20

2. A 32-Bit DSP Instruction Pipeline Control Unit Verification Method Based on Instruction Reordering Strategy;Symmetry;2022-03-22

3. Built-In Test Selection Methodology for Optimal Reliability Fault Coverage;2021 Annual Reliability and Maintainability Symposium (RAMS);2021-05-24

4. Locating Open-Channels in Octagon Networks on Chip-Microprocessors;2020 IEEE Computer Society Annual Symposium on VLSI (ISVLSI);2020-07

5. A Non-Blocking Non-Degrading Multiple Defects Link Testing Method for 3D-Networks-on-Chip;IEEE Access;2020