Author:
Etherton M.,Willemen J.,Wilkening W.,Qu N.,Mettler S.,Fichtner W.
Subject
Electrical and Electronic Engineering,Surfaces, Coatings and Films,Safety, Risk, Reliability and Quality,Condensed Matter Physics,Atomic and Molecular Physics, and Optics,Electronic, Optical and Magnetic Materials
Reference13 articles.
1. Advanced CMOS protection device trigger mechanisms during CDM;Duvvury;IEEE Trans Compon, Pack, Manuf Technol,1996
2. Circuit-level simulation of CDM–ESD and EOS in submicron MOS devices;Ramaswamy;Proc EOS/ESD Symp,1996
3. Grounded-gate nMOS transistor behavior under CDM ESD stress conditions;Verhage;IEEE Trans Electron Dev,1997
4. ESD-level circuit simulation – impact of gate RC-delay on HBM and CDM behavior;Mergens;Proc EOS/ESD Symp,2000
5. Influence of tester parasitics on ‘charged device model’ – failure thresholds;Gieser;Proc EOS/ESD Symp,1994