ESD–RF co-design methodology for the state of the art RF-CMOS blocks-Reference-Cited by-同舟云学术

ESD–RF co-design methodology for the state of the art RF-CMOS blocks

Published:2005-02 Issue:2 Volume:45 Page:255-268
ISSN:0026-2714
Container-title:Microelectronics Reliability
language:en
Short-container-title:Microelectronics Reliability

Author:

Vassilev V.,Thijs S.,Segura P.L.,Wambacq P.,Leroux P.,Groeseneken G.,Natarajan M.I.,Maes H.E.,Steyaert M.

Publisher

Elsevier BV

Subject

Electrical and Electronic Engineering,Surfaces, Coatings and Films,Safety, Risk, Reliability and Quality,Condensed Matter Physics,Atomic and Molecular Physics, and Optics,Electronic, Optical and Magnetic Materials

Reference14 articles.

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3. A study of the parasitic effects of ESD protection on RF ICs;Gong;Proc. IEEE Tran. Microwave Theory Tech.,2002

4. Richier C et al. Investigation on different ESD protection strategies devoted to 3.3V RF applications in a 0.18 CMOS process. In: Proc EOS/ESD Symp, 2000. p. 251–9

5. Worley E et al. Optimization of input protection diode for high speed applications. In: Proc EOS/ESD Symp, 2002. p. 62–72

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