Optimizing the hot carrier reliability of N-LDMOS transistor arrays-Reference-Cited by-同舟云学术

Optimizing the hot carrier reliability of N-LDMOS transistor arrays

Published:2005-07 Issue:7-8 Volume:45 Page:1021-1032
ISSN:0026-2714
Container-title:Microelectronics Reliability
language:en
Short-container-title:Microelectronics Reliability

Author:

Brisbin Douglas,Strachan Andy,Chaparala Prasad

Publisher

Elsevier BV

Subject

Electrical and Electronic Engineering,Surfaces, Coatings and Films,Safety, Risk, Reliability and Quality,Condensed Matter Physics,Atomic and Molecular Physics, and Optics,Electronic, Optical and Magnetic Materials

Reference29 articles.

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3. The optimization of LBC6 power/mixed-signal BiCMOS process;Nehrer;BCTM,2001

4. LDMOS implementation in a 0.35μm BCD technology (BCD6);Moscatelli;ISPSD,2000

5. Complementary 25V LDMOS for analog applications based on 0.6μm BiCMOS technology;Nakamura;BCTM,2000

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1. Performance Evaluation Study of MOSFET Devices After S-band Pulsed-RF Accelerated Tests;2021 International Conference on Engineering and Emerging Technologies (ICEET);2021-10-27

2. A Review on Hot-Carrier-Induced Degradation of Lateral DMOS Transistor;IEEE Transactions on Device and Materials Reliability;2018-06

3. Evolution study of the ElectroMagnetic Interference for RF LDMOS in series chopper application after thermal accelerated tests;Microelectronics Reliability;2016-09

4. Analysis of high-voltage metal–oxide–semiconductor transistors with gradual junction in the drift region;Japanese Journal of Applied Physics;2016-07-07

5. Impact of hot carrier injection on switching time evolution for power RF LDMOS after accelerated tests;Microelectronics Reliability;2015-08